A semiconductor memory device is a general term for storage media that are used to store data in computers or communication equipments. Semiconductor memory devices are classified into DRAM devices, SRAM devices, flash memory devices and ROM devices according to their data storage methods, and the DRAM devices are being most widely used among them.
FIGS. 1 and 2 are block diagrams illustrating known integrated circuits. FIG. 3 is a timing diagram illustrating an operation of the integrated circuit illustrated in FIG. 1. FIG. 4 is a timing diagram illustrating an operation of the integrated circuit illustrated in FIG. 2.
According to data storage capacity, an integrated circuit may include a memory controller 1 and a semiconductor memory device 2 as illustrated in FIG. 1, or may include a memory controller 3 and semiconductor memory devices 4 and 5 shared by the memory controller 3 as illustrated in FIG. 2. That is, as the integration density of an integrated circuit increases, the number of semiconductor memory devices shared by a memory controller increases as illustrated in FIG. 2.
Hereinafter, an operation of the integrated circuit illustrated in FIG. 1 will be described with reference to FIG. 3.
The semiconductor memory device 2 receives a read command RD from the memory controller 1 at time t0, and deactivates an ODT enable signal ODTEN to a low level during a time period from a time t3 to a time t7. Here, the ODT enable signal ODTEN is a signal that is activated to a high level to operate an On Die Termination (ODT) circuit. In the semiconductor memory device 2, the ODT enable signal ODTEN is deactivated to a low level during a data output time period for a read operation to interrupt an operation of the ODT circuit in order not to perform a write operation.
In the time period when the ODT enable signal is deactivated to a low level, the semiconductor 2 receives a toggling read data strobe signal RDQS and outputs data DQ1, . . . , DQ4 sequentially in synchronization with a rising edge and a falling edge of the read data strobe signal RDQS.
At the time t7 when the data output time period for a read operation ends, the semiconductor memory device 2 which has received a write command WT from the memory controller 1, generates a write enable signal WTEN activated to a high level for a write operation, and receives a toggling write data strobe signal WDQS from the memory controller 1 in response to the write enable signal WTEN. The semiconductor memory device 2 receives data DQ5, . . . , DQ8 sequentially in synchronization with a rising edge and a falling edge of the write data strobe signal WDQS.
Hereinafter, an operation of the integrated circuit illustrated in FIG. 2 will be described with reference to FIG. 4.
The semiconductor memory device 4 receives a read command RD from the memory controller 3 at time t0, and deactivates a first ODT enable signal ODTEN1 to a low level during a time period from a time t3 to a time t7. Here, the first ODT enable signal ODTEN1 is a signal that is activated to a high level to operate an On Die Temination (ODT) circuit included in the semiconductor memory device 4. In the semiconductor memory device 4, the first ODT enable signal ODTEN1 is deactivated to a low level in a data output time period for a read operation to interrupt an operation of the ODT circuit in order not to perform a write operation.
On the other hand, the semiconductor memory device 5 receives a snoop read command SRD from the memory controller 3 at time t0, and deactivates a second ODT enable signal ODTEN2 to a low level during the time period from the time t3 to the time t7. Here, the second ODT enable signal ODTEN2 is a signal that is activated to a high level to operate an On Die Temination (ODT) circuit included in the semiconductor memory device 5. In the semiconductor memory device 5, the second ODT enable signal ODTEN2 is deactivated to a low level during a data output time period for a read operation to interrupt an operation of the ODT circuit in order not to perform a write operation.
The reason for applying the snoop read command SRD, to the semiconductor memory device 5 not performing a read operation, is to prevent the semiconductor memory device 5 from performing a write operation during the data output time period in the read operation of the semiconductor memory device 4.
As described above, when the semiconductor memory device 4 performs a read operation, the first ODT enable signal ODTEN1 and the second ODT enable signal ODTEN2 are deactivated to a low level during the data output time period for a read operation to prevent the semiconductor memory devices 4 and 5 from performing a write operation.
However, there is a case where a false write command is applied to the semiconductor memory device 4 of the semiconductor memory device 5 due to a channel/power noise during the time period from time t0 to time t3, at which the read command RD is inputted. In this case, a malfunction may occur because a write operation of the semiconductor memory device 4 or the semiconductor memory device 5 is performed during the data output time period in the read operation of the semiconductor memory device 4.